Semiconductor device including a superlattice and replacement metal gate structure and related methods

ABSTRACT

A semiconductor device may include a substrate having a channel recess therein, a plurality of spaced apart shallow trench isolation (STI) regions in the substrate, and source and drain regions spaced apart in the substrate and between a pair of the STI regions. A superlattice channel may be in the channel recess of the substrate and extend between the source and drain regions, with the superlattice channel including a plurality of stacked group of layers, and each group of layers of the superlattice channel including stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A replacement gate may be over the superlattice channel.

RELATED APPLICATIONS

This application is based upon prior filed provisional application Ser. No. 62/083,994 filed Nov. 25, 2014; the disclosures of which are incorporated herein by reference in its entirety.

FIELD OF THE INVENTION

The present invention relates to the field of semiconductors, and, more particularly, to semiconductor devices comprising superlattices and associated methods.

BACKGROUND OF THE INVENTION

Structures and techniques have been proposed to enhance the performance of semiconductor devices, such as by enhancing the mobility of the charge carriers. For example, U.S. Patent Application No. 2003/0057416 to Currie et al. discloses strained material layers of silicon, silicon-germanium, and relaxed silicon and also including impurity-free zones that would otherwise cause performance degradation. The resulting biaxial strain in the upper silicon layer alters the carrier mobilities enabling higher speed and/or lower power devices. Published U.S. Patent Application No. 2003/0034529 to Fitzgerald et al. discloses a CMOS inverter also based upon similar strained silicon technology.

U.S. Pat. No. 6,472,685 B2 to Takagi discloses a semiconductor device including a silicon and carbon layer sandwiched between silicon layers so that the conduction band and valence band of the second silicon layer receive a tensile strain. Electrons having a smaller effective mass, and which have been induced by an electric field applied to the gate electrode, are confined in the second silicon layer, thus, an n-channel MOSFET is asserted to have a higher mobility.

U.S. Pat. No. 4,937,204 to Ishibashi et al. discloses a superlattice in which a plurality of layers, less than eight monolayers, and containing a fractional or binary or a binary compound semiconductor layer, are alternately and epitaxially grown. The direction of main current flow is perpendicular to the layers of the superlattice.

U.S. Pat. No. 5,357,119 to Wang et al. discloses a Si—Ge short period superlattice with higher mobility achieved by reducing alloy scattering in the superlattice. Along these lines, U.S. Pat. No. 5,683,934 to Candelaria discloses an enhanced mobility MOSFET including a channel layer comprising an alloy of silicon and a second material substitutionally present in the silicon lattice at a percentage that places the channel layer under tensile stress.

U.S. Pat. No. 5,216,262 to Tsu discloses a quantum well structure comprising two barrier regions and a thin epitaxially grown semiconductor layer sandwiched between the barriers. Each barrier region consists of alternate layers of SiO₂/Si with a thickness generally in a range of two to six monolayers. A much thicker section of silicon is sandwiched between the barriers.

An article entitled “Phenomena in silicon nanostructure devices” also to Tsu and published online Sep. 6, 2000 by Applied Physics and Materials Science & Processing, pp. 391-402 discloses a semiconductor-atomic superlattice (SAS) of silicon and oxygen. The Si/0 superlattice is disclosed as useful in a silicon quantum and light-emitting devices. In particular, a green electromuminescence diode structure was constructed and tested. Current flow in the diode structure is vertical, that is, perpendicular to the layers of the SAS. The disclosed SAS may include semiconductor layers separated by adsorbed species such as oxygen atoms, and CO molecules. The silicon growth beyond the adsorbed monolayer of oxygen is described as epitaxial with a fairly low defect density. One SAS structure included a 1.1 nm thick silicon portion that is about eight atomic layers of silicon, and another structure had twice this thickness of silicon. An article to Luo et al. entitled “Chemical Design of Direct-Gap Light-Emitting Silicon” published in Physical Review Letters, Vol. 89, No. 7 (Aug. 12, 2002) further discusses the light emitting SAS structures of Tsu.

Published International Application WO 02/103,767 Al to Wang, Tsu and Lofgren, discloses a barrier building block of thin silicon and oxygen, carbon, nitrogen, phosphorous, antimony, arsenic or hydrogen to thereby reduce current flowing vertically through the lattice more than four orders of magnitude. The insulating layer/barrier layer allows for low defect epitaxial silicon to be deposited next to the insulating layer. Published Great Britain Patent Application 2,347,520 to Mears et al. discloses that principles of Aperiodic Photonic Band-Gap (APBG) structures may be adapted for electronic bandgap engineering. In particular, the application discloses that material parameters, for example, the location of band minima, effective mass, etc, can be tailored to yield new aperiodic materials with desirable band-structure characteristics. Other parameters, such as electrical conductivity, thermal conductivity and dielectric permittivity or magnetic permeability are disclosed as also possible to be designed into the material.

Despite the advantages provided by such structures, further developments may be desirable for integrating advanced semiconductor materials in various semiconductor devices.

SUMMARY

A method for making a semiconductor device may include forming a plurality of spaced apart shallow trench isolation (STI) regions in a substrate, forming a dummy gate on the substrate between a pair of the STI regions, forming source and drain regions in the substrate on opposing sides of the dummy gate and between the pair of STI regions, and forming a dielectric layer on the substrate surrounding the dummy gate. The method may further include removing the dummy gate and portions of the substrate beneath the dummy gate to define a channel recess in the substrate between the source and drain regions, and forming a superlattice channel in the channel recess including a plurality of stacked group of layers. Each group of layers of the superlattice channel may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may also include forming a replacement gate over the superlattice channel and removing the dielectric layer.

More particularly, the method may further include performing a well implant in the substrate between the pair of STI regions. Also, forming the replacement gate may include forming a high K dielectric layer over the superlattice channel, and forming a metal gate electrode over the high K dielectric layer.

By way of example, each base semiconductor portion may comprise silicon, germanium, etc. Also by way of example, the at least one non-semiconductor monolayer may comprise a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.

In addition, the superlattice channel may further include a base semiconductor cap layer on an uppermost group of layers. Moreover, at least some semiconductor atoms from opposing base semiconductor portions may be chemically bound together through the at least one non-semiconductor monolayer therebetween.

A related semiconductor device may include a substrate having a channel recess therein, a plurality of spaced apart shallow trench isolation (STI) regions in the substrate, and source and drain regions spaced apart in the substrate and between a pair of the STI regions. A superlattice channel may be in the channel recess of the substrate and extend between the source and drain regions, with the superlattice channel including a plurality of stacked group of layers, and each group of layers of the superlattice channel comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A replacement gate may be over the superlattice channel.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a greatly enlarged schematic cross-sectional view of a superlattice for use in a semiconductor device in accordance with the present invention.

FIG. 2 is a perspective schematic atomic diagram of a portion of the superlattice shown in FIG. 1.

FIG. 3 is a greatly enlarged schematic cross-sectional view of another embodiment of a superlattice in accordance with the invention.

FIG. 4A is a graph of the calculated band structure from the gamma point (G) for both bulk silicon as in the prior art, and for the 4/1 Si/O superlattice as shown in FIGS. 1-2.

FIG. 4B is a graph of the calculated band structure from the Z point for both bulk silicon as in the prior art, and for the 4/1 Si/O superlattice as shown in FIGS. 1-2.

FIG. 4C is a graph of the calculated band structure from both the gamma and Z points for both bulk silicon as in the prior art, and for the 5/1/3/1 Si/O superlattice as shown in FIG. 3.

FIG. 5 is a cross-sectional diagram of a semiconductor device in accordance with an example embodiment including a replacement metal gate overlying a superlattice channel layer.

FIGS. 6-13 are a series of cross-sectional diagrams illustrating a method for making the semiconductor device of FIG. 5.

FIG. 14 is a flow diagram corresponding to the method illustrated in FIGS. 5-13.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout, and prime notation is used to indicate similar elements in different embodiments.

The present invention relates to controlling the properties of semiconductor materials at the atomic or molecular level. Further, the invention relates to the identification, creation, and use of improved materials for use in semiconductor devices.

Applicants theorize, without wishing to be bound thereto, that certain superlattices as described herein reduce the effective mass of charge carriers and that this thereby leads to higher charge carrier mobility. Effective mass is described with various definitions in the literature. As a measure of the improvement in effective mass Applicants use a “conductivity reciprocal effective mass tensor”, M_(e) ⁻¹and m_(h) ⁻¹ for electrons and holes respectively, defined as:

${M_{e,{ij}}^{- 1}\left( {E_{F},T} \right)} = \frac{\sum\limits_{E > E_{F}}{\int\limits_{B.Z.}{\left( {\nabla_{k}{E\left( {k,n} \right)}} \right)_{i}\left( {\nabla_{k}{E\left( {k,n} \right)}} \right)_{j}\frac{\partial{f\left( {{E\left( {k,n} \right)},E_{F},T} \right)}}{\partial E}d^{3}k}}}{\sum\limits_{E > E_{F}}{\int\limits_{B.Z.}{{f\left( {{E\left( {k,n} \right)},E_{F},T} \right)}d^{3}k}}}$

for electrons and:

${M_{h,{ij}}^{- 1}\left( {E_{F},T} \right)} = \frac{- {\sum\limits_{E < E_{F}}{\int\limits_{B.Z.}{\left( {\nabla_{k}{E\left( {k,n} \right)}} \right)_{i}\left( {\nabla_{k}{E\left( {k,n} \right)}} \right)_{j}\frac{\partial{f\left( {{E\left( {k,n} \right)},E_{F},T} \right)}}{\partial E}d^{3}k}}}}{\sum\limits_{E < E_{F}}{\int\limits_{B.Z.}{\left( {1 - {f\left( {{E\left( {k,n} \right)},E_{F},T} \right)}} \right)d^{3}k}}}$

for holes, where f is the Fermi-Dirac distribution, E_(F) is the Fermi energy, T is the temperature, E(k,n) is the energy of an electron in the state corresponding to wave vector k and the n^(th) energy band, the indices i and j refer to Cartesian coordinates x, y and z, the integrals are taken over the Brillouin zone (B.Z.), and the summations are taken over bands with energies above and below the Fermi energy for electrons and holes respectively.

Applicants' definition of the conductivity reciprocal effective mass tensor is such that a tensorial component of the conductivity of the material is greater for greater values of the corresponding component of the conductivity reciprocal effective mass tensor. Again Applicants theorize without wishing to be bound thereto that the superlattices described herein set the values of the conductivity reciprocal effective mass tensor so as to enhance the conductive properties of the material, such as typically for a preferred direction of charge carrier transport. The inverse of the appropriate tensor element is referred to as the conductivity effective mass. In other words, to characterize semiconductor material structures, the conductivity effective mass for electrons/holes as described above and calculated in the direction of intended carrier transport is used to distinguish improved materials.

Applicants have identified improved materials or structures for use in semiconductor devices. More specifically, the Applicants have identified materials or structures having energy band structures for which the appropriate conductivity effective masses for electrons and/or holes are substantially less than the corresponding values for silicon. In addition to the enhanced mobility characteristics of these structures, they may also be formed or used in such a manner that they provide piezoelectric, pyroelectric, and/or ferroelectric properties that are advantageous for use in a variety of different types of devices, as will be discussed further below.

Referring now to FIGS. 1 and 2, the materials or structures are in the form of a superlattice 25 whose structure is controlled at the atomic or molecular level and may be formed using known techniques of atomic or molecular layer deposition. The superlattice 25 includes a plurality of layer groups 45 a-45 n arranged in stacked relation, as perhaps best understood with specific reference to the schematic cross-sectional view of FIG. 1.

Each group of layers 45 a-45 n of the superlattice 25 illustratively includes a plurality of stacked base semiconductor monolayers 46 defining a respective base semiconductor portion 46 a-46 n and an energy band-modifying layer 50 thereon. The energy band-modifying layers 50 are indicated by stippling in FIG. 1 for clarity of illustration.

The energy band-modifying layer 50 illustratively includes one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. By “constrained within a crystal lattice of adjacent base semiconductor portions” it is meant that at least some semiconductor atoms from opposing base semiconductor portions 46 a-46 n are chemically bound together through the non-semiconductor monolayer 50 therebetween, as seen in FIG. 2. Generally speaking, this configuration is made possible by controlling the amount of non-semiconductor material that is deposited on semiconductor portions 46 a-46 n through atomic layer deposition techniques so that not all (i.e., less than full or 100% coverage) of the available semiconductor bonding sites are populated with bonds to non-semiconductor atoms, as will be discussed further below. Thus, as further monolayers 46 of semiconductor material are deposited on or over a non-semiconductor monolayer 50, the newly deposited semiconductor atoms will populate the remaining vacant bonding sites of the semiconductor atoms below the non-semiconductor monolayer.

In other embodiments, more than one such non-semiconductor monolayer may be possible. It should be noted that reference herein to a non-semiconductor or semiconductor monolayer means that the material used for the monolayer would be a non-semiconductor or semiconductor if formed in bulk. That is, a single monolayer of a material, such as silicon, may not necessarily exhibit the same properties that it would if formed in bulk or in a relatively thick layer, as will be appreciated by those skilled in the art.

Applicants theorize without wishing to be bound thereto that energy band-modifying layers 50 and adjacent base semiconductor portions 46 a-46 n cause the superlattice 25 to have a lower appropriate conductivity effective mass for the charge carriers in the parallel layer direction than would otherwise be present. Considered another way, this parallel direction is orthogonal to the stacking direction. The band modifying layers 50 may also cause the superlattice 25 to have a common energy band structure, while also advantageously functioning as an insulator between layers or regions vertically above and below the superlattice.

Moreover, this superlattice structure may also advantageously act as a barrier to dopant and/or material diffusion between layers vertically above and below the superlattice 25. These properties may thus advantageously allow the superlattice 25 to provide an interface for high-K dielectrics which not only reduces diffusion of the high-K material into the channel region, but which may also advantageously reduce unwanted scattering effects and improve device mobility, as will be appreciated by those skilled in the art.

It is also theorized that semiconductor devices including the superlattice 25 may enjoy a higher charge carrier mobility based upon the lower conductivity effective mass than would otherwise be present. In some embodiments, and as a result of the band engineering achieved by the present invention, the superlattice 25 may further have a substantially direct energy bandgap that may be particularly advantageous for opto-electronic devices, for example.

The superlattice 25 also illustratively includes a cap layer 52 on an upper layer group 45 n. The cap layer 52 may comprise a plurality of base semiconductor monolayers 46. The cap layer 52 may have between 2 to 100 monolayers of the base semiconductor, and, more preferably between 10 to 50 monolayers.

Each base semiconductor portion 46 a-46 n may comprise a base semiconductor selected from the group consisting of Group IV semiconductors, Group III-V semiconductors, and Group II-VI semiconductors. Of course, the term Group IV semiconductors also includes Group IV-IV semiconductors, as will be appreciated by those skilled in the art. More particularly, the base semiconductor may comprise at least one of silicon and germanium, for example.

Each energy band-modifying layer 50 may comprise a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, carbon and carbon-oxygen, for example. The non-semiconductor is also desirably thermally stable through deposition of a next layer to thereby facilitate manufacturing. In other embodiments, the non-semiconductor may be another inorganic or organic element or compound that is compatible with the given semiconductor processing as will be appreciated by those skilled in the art. More particularly, the base semiconductor may comprise at least one of silicon and germanium, for example

It should be noted that the term monolayer is meant to include a single atomic layer and also a single molecular layer. It is also noted that the energy band-modifying layer 50 provided by a single monolayer is also meant to include a monolayer wherein not all of the possible sites are occupied (i.e., there is less than full or 100% coverage). For example, with particular reference to the atomic diagram of FIG. 2, a 4/1 repeating structure is illustrated for silicon as the base semiconductor material, and oxygen as the energy band-modifying material. Only half of the possible sites for oxygen are occupied in the illustrated example.

In other embodiments and/or with different materials this one-half occupation would not necessarily be the case as will be appreciated by those skilled in the art. Indeed it can be seen even in this schematic diagram, that individual atoms of oxygen in a given monolayer are not precisely aligned along a flat plane as will also be appreciated by those of skill in the art of atomic deposition. By way of example, a preferred occupation range is from about one-eighth to one-half of the possible oxygen sites being full, although other numbers may be used in certain embodiments.

Silicon and oxygen are currently widely used in conventional semiconductor processing, and, hence, manufacturers will be readily able to use these materials as described herein. Atomic or monolayer deposition is also now widely used. Accordingly, semiconductor devices incorporating the superlattice 25 in accordance with the invention may be readily adopted and implemented, as will be appreciated by those skilled in the art.

It is theorized without Applicants wishing to be bound thereto that for a superlattice, such as the Si/O superlattice, for example, that the number of silicon monolayers should desirably be seven or less so that the energy band of the superlattice is common or relatively uniform throughout to achieve the desired advantages. The 4/1 repeating structure shown in FIGS. 1 and 2, for Si/O has been modeled to indicate an enhanced mobility for electrons and holes in the X direction. For example, the calculated conductivity effective mass for electrons (isotropic for bulk silicon) is 0.26 and for the 4/1 SiO superlattice in the X direction it is 0.12 resulting in a ratio of 0.46. Similarly, the calculation for holes yields values of 0.36 for bulk silicon and 0.16 for the 4/1 Si/O superlattice resulting in a ratio of 0.44.

While such a directionally preferential feature may be desired in certain semiconductor devices, other devices may benefit from a more uniform increase in mobility in any direction parallel to the groups of layers. It may also be beneficial to have an increased mobility for both electrons or holes, or just one of these types of charge carriers as will be appreciated by those skilled in the art.

The lower conductivity effective mass for the 4/1 Si/O embodiment of the superlattice 25 may be less than two-thirds the conductivity effective mass than would otherwise occur, and this applies for both electrons and holes. Of course, the superlattice 25 may further comprise at least one type of conductivity dopant therein, as will also be appreciated by those skilled in the art.

Indeed, referring now additionally to FIG. 3, another embodiment of a superlattice 25′ in accordance with the invention having different properties is now described. In this embodiment, a repeating pattern of 3/1/5/1 is illustrated. More particularly, the lowest base semiconductor portion 46 a′ has three monolayers, and the second lowest base semiconductor portion 46 b′ has five monolayers. This pattern repeats throughout the superlattice 25′. The energy band-modifying layers 50′ may each include a single monolayer. For such a superlattice 25′ including Si/O, the enhancement of charge carrier mobility is independent of orientation in the plane of the layers. Those other elements of FIG. 3 not specifically mentioned are similar to those discussed above with reference to FIG. 1 and need no further discussion herein.

In some device embodiments, all of the base semiconductor portions of a superlattice may be a same number of monolayers thick. In other embodiments, at least some of the base semiconductor portions may be a different number of monolayers thick. In still other embodiments, all of the base semiconductor portions may be a different number of monolayers thick.

In FIGS. 4A-4C, band structures calculated using Density Functional Theory (DFT) are presented. It is well known in the art that DFT underestimates the absolute value of the bandgap. Hence all bands above the gap may be shifted by an appropriate “scissors correction.” However the shape of the band is known to be much more reliable. The vertical energy axes should be interpreted in this light.

FIG. 4A shows the calculated band structure from the gamma point (G) for both bulk silicon (represented by continuous lines) and for the 4/1 Si/O superlattice 25 shown in FIG. 1 (represented by dotted lines). The directions refer to the unit cell of the 4/1 Si/O structure and not to the conventional unit cell of Si, although the (001) direction in the figure does correspond to the (001) direction of the conventional unit cell of Si, and, hence, shows the expected location of the Si conduction band minimum. The (100) and (010) directions in the figure correspond to the (110) and (−110) directions of the conventional Si unit cell. Those skilled in the art will appreciate that the bands of Si on the figure are folded to represent them on the appropriate reciprocal lattice directions for the 4/1 Si/O structure.

It can be seen that the conduction band minimum for the 4/1 Si/O structure is located at the gamma point in contrast to bulk silicon (Si), whereas the valence band minimum occurs at the edge of the Brillouin zone in the (001) direction which we refer to as the Z point. One may also note the greater curvature of the conduction band minimum for the 4/1 Si/O structure compared to the curvature of the conduction band minimum for Si owing to the band splitting due to the perturbation introduced by the additional oxygen layer.

FIG. 4B shows the calculated band structure from the Z point for both bulk silicon (continuous lines) and for the 4/1 Si/O superlattice 25 (dotted lines). This figure illustrates the enhanced curvature of the valence band in the (100) direction.

FIG. 4C shows the calculated band structure from both the gamma and Z point for both bulk silicon (continuous lines) and for the 5/1/3/1 Si/O structure of the superlattice 25′ of FIG. 3 (dotted lines). Due to the symmetry of the 5/1/3/1 Si/O structure, the calculated band structures in the (100) and (010) directions are equivalent. Thus the conductivity effective mass and mobility are expected to be isotropic in the plane parallel to the layers, i.e. perpendicular to the (001) stacking direction. Note that in the 5/1/3/1 Si/O example the conduction band minimum and the valence band maximum are both at or close to the Z point.

Although increased curvature is an indication of reduced effective mass, the appropriate comparison and discrimination may be made via the conductivity reciprocal effective mass tensor calculation. This leads Applicants to further theorize that the 5/1/3/1 superlattice 25′ should be substantially direct bandgap. As will be understood by those skilled in the art, the appropriate matrix element for optical transition is another indicator of the distinction between direct and indirect bandgap behavior.

Using the above-described measures, one can select materials having improved band structures for specific purposes. One such example would be a superlattice material layer 125 in a semiconductor device 100 in which the superlattice material is positioned in a channel recess 104 beneath a replacement gate 105, as shown in FIG. 5. The above-described quantum confinement properties of the superlattice material layer 125 when utilized in the channel region of the semiconductor device 100 may provide significant advantages, such as bias temperature instability (BTI) reliability improvement, as well as carrier mobility boost (and, accordingly, NMOS performance improvement), as well as providing a “channel last” integration option, meaning that the channel is formed after the source/drain and dummy gate formation, as will be discussed further below. Moreover, as also described above, the superlattice material may also help reduce leakage in the channel region as well.

In the illustrated example, the semiconductor device 100 is a planar MOSFET device, which may be used for NMOS, PMOS, or CMOS devices, for example. However, it should be noted that the superlattice/gate structure shown in FIG. 5 may be used in other configurations as well, such as vertical devices (e.g., FINFETs, etc.). The semiconductor device 100 illustratively includes a silicon substrate 106, spaced apart source and drain regions 107, 108 in the substrate, and the superlattice material layer 125 which is positioned between the source and drain regions in the channel recess 104 of the substrate. Shallow trench isolation (STI) regions 109 may be included to insulate the source and drain regions 107, 108 from other devices on the substrate 106, as will be appreciated by those skilled in the art. In the illustrated example, the gate 105 is a high K replacement metal gate including a metal gate electrode 110 and a high K dielectric layer 111, and is positioned over the superlattice channel layer 125 laterally between the source and drain regions 107, 108, as shown. The channel of the device 100 may be defined fully or partially within the superlattice channel layer 125, or it may also extend beneath the superlattice channel layer in some embodiments.

An example method for making the semiconductor device 100 will now be described with reference to FIGS. 6-14. STI and well module preparation may be performed at Blocks 201-202 to form the starting substrate or wafer (FIG. 6), as will be appreciated by those skilled in the art. A “dummy gate” 113 may then be formed on the substrate 106 overlying what is to become the channel region, at Block 203 (FIG. 6). More particularly, the dummy gate 113 formation may include forming a blanket polycrystalline semiconductor layer 112 (e.g., polysilicon) over the substrate 106 and STI regions 109 (FIG. 7), and then patterning the polycrystalline layer to define the dummy gate 113 (FIG. 8). The dummy gate 113 may then be used to align the source and drain 107, 108 implants, at Block 204 (FIG. 9).

A dielectric layer 114 (e.g., SiO₂) may be formed overlying the source and drain regions 107, 108 and the STI regions 109 and surrounding the dummy gate 113, as seen in FIG. 10. The dummy gate 113 may then be removed (Block 205) to make way for the replacement metal gate 105. Moreover, etching of the dummy gate 113 may extend down into the substrate 106 to create the channel recess 104, as seen in FIG. 11. The superlattice layer 125 may then be formed in the channel recess 104 using the above-described techniques and configurations, at Block 206, as seen in FIG. 12. The replacement metal gate 105 may then be formed by depositing the high K dielectric layer 111, and the metal gate electrode 110, as seen in FIG. 13 (Block 207), as will be appreciated by those skilled in the art. Further semiconductor device processing may then be performed as appropriate for the given device type, as will be appreciated by those skilled in the art. For example, the dielectric layer 114 may be removed, and respective source/drain contacts 127, 128 may be formed, as seen in FIG. 5, for example.

The foregoing metal gate implementation may accordingly not only provide the above-noted advantages of BTI reliability improvement and carrier mobility boost, but it may also provide integration flexibility in terms of gate formation and channel integration. As noted above, the superlattice channel layer 125 may advantageously be formed after the source and drain 107, 108 formation, which may be desirable in that the superlattice channel layer is not subjected to the various processing steps associated with the source/drain formation and dummy gate 113 processing. Moreover, the above-described steps could be re-ordered to provide for a “gate first” option, rather than the exemplary “gate last” approach set forth above. Such processing flexibility may be advantageous for CMOS implementations at 32 nm nodes or below, for example, although the configurations described herein may be used with other device sizes as well.

Many modifications and other embodiments will come to the mind of one skilled in the art having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is understood that the invention is not to be limited to the specific embodiments disclosed, and that modifications and embodiments are intended to be included within the scope of the present disclosure and the following claims. 

That which is claimed is:
 1. A method for making a semiconductor device comprising: forming a plurality of spaced apart shallow trench isolation (STI) regions in a substrate; forming a dummy gate on the substrate between a pair of the STI regions; forming source and drain regions in the substrate on opposing sides of the dummy gate and between the pair of STI regions; forming a dielectric layer on the substrate surrounding the dummy gate; removing the dummy gate and portions of the substrate beneath the dummy gate to define a channel recess in the substrate between the source and drain regions; forming a superlattice channel in the channel recess including a plurality of stacked groups of layers, each group of layers of the superlattice channel comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions; and forming a replacement gate over the superlattice channel and removing the dielectric layer.
 2. The method of claim 1 further comprising performing a well implant in the substrate between the pair of STI regions.
 3. The method of claim 1 wherein forming the replacement gate comprises forming a high K dielectric layer over the superlattice channel, and forming a metal gate electrode over the high K dielectric layer.
 4. The method of claim 1 wherein each base semiconductor portion comprises silicon.
 5. The method of claim 1 wherein each base semiconductor portion comprises germanium.
 6. The method of claim 1 wherein the at least one non-semiconductor layer comprises oxygen.
 7. The method of claim 1 wherein the at least one non-semiconductor monolayer comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.
 8. The method of claim 1 wherein the superlattice channel further comprises a base semiconductor cap layer on an uppermost group of layers.
 9. The method of claim 1 wherein at least some semiconductor atoms from opposing base semiconductor portions are chemically bound together through the at least one non-semiconductor monolayer therebetween.
 10. A semiconductor device comprising: a substrate having a channel recess therein; a plurality of spaced apart shallow trench isolation (STI) regions in said substrate; source and drain regions spaced apart in the substrate and between a pair of the STI regions; and a superlattice channel in the channel recess of said substrate and extending between the source and drain regions, the superlattice channel including a plurality of stacked groups of layers, each group of layers of the superlattice channel comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions; and a replacement gate over the superlattice channel.
 11. The semiconductor device of claim 10 further comprising a well implant in the substrate between the pair of STI regions.
 12. The semiconductor device of claim 10 wherein the replacement gate comprises: a high K dielectric layer over the superlattice channel; and a metal gate electrode over the high K dielectric layer.
 13. The semiconductor device of claim 10 wherein each base semiconductor portion comprises silicon.
 14. The semiconductor device of claim 10 wherein each base semiconductor portion comprises germanium.
 15. The semiconductor device of claim 10 wherein the at least one non-semiconductor layer comprises oxygen.
 16. The semiconductor device of claim 10 wherein the at least one non-semiconductor monolayer comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.
 17. The semiconductor device of claim 10 wherein the superlattice channel further comprises a base semiconductor cap layer on an uppermost group of layers.
 18. The semiconductor device of claim 10 wherein at least some semiconductor atoms from opposing base semiconductor portions are chemically bound together through the at least one non-semiconductor monolayer therebetween.
 19. A semiconductor device comprising: a substrate having a channel recess therein; a plurality of spaced apart shallow trench isolation (STI) regions in said substrate; source and drain regions spaced apart in the substrate and between a pair of the STI regions; a superlattice channel in the channel recess of said substrate and extending between the source and drain regions, the superlattice channel including a plurality of stacked groups of layers, each group of layers of the superlattice channel comprising a plurality of stacked silicon monolayers defining a base silicon portion and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions; and a replacement gate comprising a high K dielectric layer over the superlattice channel and a metal gate electrode over the high K dielectric layer.
 20. The semiconductor device of claim 19 further comprising a well implant in the substrate between the pair of STI regions.
 21. The semiconductor device of claim 19 wherein the superlattice channel further comprises a base silicon cap layer on an uppermost group of layers.
 22. The semiconductor device of claim 19 wherein at least some semiconductor atoms from opposing base silicon portions are chemically bound together through the at least one oxygen monolayer therebetween. 